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| Preliminary Technical Data FEATURES Large, 32 x 32 High Speed, Nonblocking Switch Array G = 1 (AD8117) or G = 2 (AD8118) Operation Differential or Single-Ended Operation Single +5 V supply, or dual 2.5 V supply Serial or Parallel Programming of Switch Array High impedance output disable allows connection of multiple devices with minimal output bus load Excellent Video Performance 100 MHz 0.1 dB Gain Flatness 0.1% Differential Gain Error (RL = 150 ) 0.1 Differential Phase Error (RL = 150 ) Excellent AC Performance Bandwidth: >500 MHz Slew rate: 1,800 V/s Low power of 2.5 W Low all hostile crosstalk: -75 dB @ 5 MHz -40 dB @ 500 MHz Reset pin allows disabling of all outputs (Connected through a capacitor to ground provides power-on reset capability) 304 ball SBGA package (31 mm x 31 mm) WE 500 MHz, 32 x 32 Buffered Video Crosspoint Switch AD8117/AD8118 FUNCTIONAL BLOCK DIAGRAM SER/PAR D0 D1 D2 D3 D4 D5 VDD DGND A0 A1 A2 A3 1 CLK DATA IN 0 192-BIT SHIFT REGISTER WITH 6-BIT PARALLEL LOADING 192 UPDATE RESET PARALLEL LATCH A4 DATA OUT AD8117 (AD8118) 192 32 x DECODE 6:32 DECODERS OUTPUT BUFFER G = +1 32 INPUT RECEIVER G = +1 (G = +2) 2 1024 2 SWITCH MATRIX 32 INPUT PAIRS 32 OUTPUT PAIRS APPLICATIONS Routing of high speed signals including: RGB and component video routing Compressed video (MPEG, Wavelet) Data communications VPOS VNEG VOCM Figure 1. AD8117 G = +1 PRODUCT DESCRIPTION The AD8117/AD8118 is a high speed 32 x 32 video crosspoint switch matrix. It offers a 500 MHz bandwidth and slew rate of 1800 V/s for high resolution computer graphics (RGB) signal switching. With -75 dB of crosstalk and -100 dB isolation (@ 5 MHz), the AD8117 is useful in many high-speed applications. The 0.1 dB flatness out to 100 MHz makes the AD8117 ideal for composite video switching. The AD8117's 32 independent output buffers can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus. The AD8117 is available in gain of 1 or 2 (AD8118) for ease of use in Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. back-terminated load applications. It operates as a fully differential device or can be configured for single-ended operation. Either a single +5 V supply, or dual 2.5 V supplies can be used while consuming only 500 mA of idle current with all outputs enabled. The channel switching is performed via a double-buffered, serial digital control (which can accommodate daisy chaining of several devices) or via a parallel control allowing updating of an individual output without reprogramming the entire array. The AD8117/AD8118 is packaged in a 304 Ball BGA package and is available over the extended industrial temperature range of -40C to +85C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved. AD8117/AD8118 TABLE OF CONTENTS AD8117 Specifications..................................................................... 3 Timing Characteristics (Serial Mode) ........................................... 5 Timing Characteristics (Parallel Mode) ........................................ 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Power Dissipation......................................................................... 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Preliminary Technical Data Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 18 Applications..................................................................................... 19 Programming.............................................................................. 19 Operating Modes........................................................................ 20 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 REVISION HISTORY Revision PrA: Preliminary Datasheet Rev. PrA | Page 2 of 32 Preliminary Technical Data AD8117 SPECIFICATIONS VS = 2.5 V at TA = 25C, G = +1, RL = 100 , Differential I/O mode, unless otherwise noted. Table 1. AD8117ABPZ Parameter DYNAMIC PERFORMANCE -3 dB bandwidth Gain flatness Propagation delay Settling time Slew rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, all hostile Conditions 200 mV p-p, RL = 100 2 V p-p, RL = 100 0.1 dB, 200 mV p-p, RL = 100 0.1 dB, 2 V p-p, RL = 100 2 V p-p, RL =100 1% , 2 V step, RL = 100 2 V Step, RL = 100 , peak 2 V Step, RL = 100 , 10-90% Min Typ >500 >420 100 70 1.3 2.5 1,800 1,500 AD8117/AD8118 Max Unit MHz MHz MHz MHz ns ns V/s V/s Off isolation, input-output Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching OUTPUT CHARACTERISTICS Output impedance Output disable capacitance Output leakage current Output voltage range INPUT CHARACTERISTICS Input offset voltage Input Voltage Range Common Mode Input Voltage Range Differential Mode Common-mode rejection ratio Input capacitance Input resistance Input bias current SWITCHING CHARACTERISTICS Enable on time Switching time, 2 V step Switching transient (glitch) NTSC or PAL, RL = 150 or RL = 1k NTSC or PAL, RL = 150 or RL = 1k = 5 MHz = 10 MHz = 100 MHz = 500 MHz = 10 MHz, RL = 100 , one channel 0.01 MHz to 50 MHz RL = 100 or 150 No Load, Channel-Channel RL = 100 , Channel-Channel DC, Enabled Disabled, differential Disabled Disabled No Load Differential 0.1 0.1 -75 -70 -50 -40 -100 45 1 0.5 0.5 0.1 30 2 1 2 10 4 2 2 1 1 % Degrees dB dB dB dB dB nV/Hz % % % k pF A V p-p mV V p-p V p-p dB pF k A ns ns mV p-p = 10 MHz Any switch configuration Differential -48 2 5 3 200 20 40 50% update to 1% settling 50% settling Differential Rev. PrA | Page 3 of 32 AD8117/AD8118 POWER SUPPLIES Supply current Preliminary Technical Data VPOS, outputs enabled, no load Outputs disabled VNEG, outputs enabled, no load Outputs disabled DVDD, outputs enabled, no load VNEG, VPOS, = 1 MHz VOCM, = 1 MHz 500 210 500 220 1 4.5 to 5.5 -85 -75 Supply voltage range PSRR OPERATING TEMPERATURE RANGE Temperature range JA mA mA mA mA mA V dB dB Operating (still air) Operating (still air) -40 to +85 15 C C/W Rev. PrA | Page 4 of 32 Preliminary Technical Data TIMING CHARACTERISTICS (SERIAL MODE) Parameter Serial Data Setup Time CLK Pulsewidth Serial Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulsewidth CLK to DATA OUT Valid Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 t7 Min Limit Typ AD8117/AD8118 Max Unit ns ns ns ns ns ns ns ns s ns ns Specifications subject to change without notice. 1 CLK 0 1 DATA IN 0 OUT7 (D4) OUT7 (D3) OUT00 (D0) t2 t4 LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE t1 t3 t5 1 = LATCHED UPDATE 0 = TRANSPARENT TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t6 t7 DATA OUT Figure 2. Timing Diagram, Serial Mode Table 2. Logic Levels VIH RESET, SERPAR, CLK, DATA IN, UPDATE 2.0 V min VIL RESET, SERPAR, CLK, DATA IN, UPDATE 0.8 V max VOH DATA OUT VOL DATA OUT IIH RESET, SERPAR, CLK, DATA IN, UPDATE 20 A max IIL RESET, SERPAR, CLK, DATA IN, UPDATE -400 A max IOH DATA OUT IOL DATA OUT 2.7 V min 0.5 V max -400 A max 1 mA min Rev. PrA | Page 5 of 32 AD8117/AD8118 TIMING CHARACTERISTICS (PARALLEL MODE) Parameter Parallel Data Setup Time WE Pulsewidth Parallel Data Hold Time WE Pulse Separation WE to UPDATE Delay UPDATE Pulsewidth Propagation Delay, UPDATE to Switch On or Off WE, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 Min Preliminary Technical Data Limit Typ Max Unit ns ns ns ns ns ns ns ns ns Specifications subject to change without notice. t2 1 WE 0 t4 t1 D0-D5 A0-A4 1 0 t3 t5 1 = LATCHED UPDATE 0 = TRANSPARENT t6 Figure 3. Timing Diagram, Parallel Mode Table 3. Logic Levels VIH RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE 2.0 V min VIL RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE 0.8 V max VOH DATA OUT VOL DATA OUT IIH RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE 20 A max IIL RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE -400 A max IOH DATA OUT IOL DATA OUT disabled disabled disabled disabled Rev. PrA | Page 6 of 32 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Analog Supply Voltage (VPOS - VNEG) Digital Supply Voltage (VDD - DGND) Ground potential difference (VNEG - DGND) Maximum potential difference (VDD - VNEG) Common-Mode Analog Input Voltage Differential Analog Input Voltage Digital Input Voltage Output Voltage (Disabled Analog Output) Output Short-Circuit Duration Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating +6 V +6 V +0.5 V to -2.5 V +6 V (VNEG - 0.5 V) to (VPOS + 0.5 V) 2V VDD (VPOS - 1 V) to (VNEG + 1 V) Momentary -65C to +125C -40C to +85C 300C 150C AD8117/AD8118 THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type BGA JA 15 JC Unit C/W POWER DISSIPATION The AD8117/AD8118 are operated with 2.5 V or +5 V supplies and can drive loads down to 100 , resulting in a large range of possible power dissipations. For this reason, extra care must be taken derating the operating conditions based on ambient temperature. Packaged in a 308-lead BGA, the AD8117/AD8118 junctionto-ambient thermal impedance (JA) is 15C/W. For long-term reliability, the maximum allowed junction temperature of the die should not exceed 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. The following curve shows the range of allowed internal die power dissipations that meet these conditions over the -40C to +85C ambient temperature range. When using the table, do not include external load power in the Maximum Power calculation, but do include load current dropped on the die output transistors. 8.0 TJ = 150 C NOTE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER - Watts 7.0 6.0 5.0 4.0 15 25 35 45 55 65 AMBIENT TEMPERATURE - C 75 85 Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 7 of 32 AD8117/AD8118 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 23 vpos A vpos B vpos C in16 D ip16 E in18 F ip18 G in20 H ip20 J in22 K ip22 L in24 M ip24 N in26 P ip26 R in28 T ip28 U in30 V ip30 W vpos Y vpos AA vpos AB vpos AC vpos vpos on15 op15 on13 op13 on11 op11 on9 op9 on7 op7 on5 op5 on3 vpos vpos vpos on14 op14 on12 op12 on10 op10 on8 op8 on6 op6 on4 op4 vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg ip31 vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg in31 vneg vocm ip29 vneg dgnd in29 vneg vdd ip27 vneg d0 in27 vneg d1 ip25 vneg d2 in25 vpos d3 ip23 vpos d4 in23 vpos d5 ip21 vneg web in21 vneg updateb ip19 vneg resetb in19 vneg dgnd ip17 vneg vdd in17 vneg vocm vpos vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg vpos vpos op16 on16 op18 on18 op20 on20 op22 on22 op24 on24 op26 on26 op28 22 vpos 21 vpos 20 vpos 19 op17 18 on17 17 op19 16 on19 15 op21 14 on21 13 op23 12 on23 11 op25 10 on25 9 op27 8 on27 Preliminary Technical Data 7 op29 6 on29 5 op31 4 on31 3 vpos 2 vpos 1 vpos A on28 op30 on30 vpos vpos vpos vpos B vneg vneg vneg vpos vpos vpos vpos C vneg vneg vocm vneg vpos ip0 vpos D vocm vneg in0 ip1 E vdd vneg ip2 in1 F dgnd vneg in2 ip3 G data_out vneg ip4 in3 H clk vneg in4 ip5 J data_in vneg ip6 in5 K PRELIMINARY serbpar vpos in6 ip7 L Bottom View PRELIMINARY a4 vpos ip8 in7 M a3 vpos in8 ip9 N a2 vneg ip10 in9 P a1 vneg in10 ip11 R a0 vneg ip12 in11 T vdd vneg in12 ip13 U dgnd vneg ip14 in13 V vocm vneg in14 ip15 W vneg vneg vocm vneg vpos vpos in15 Y vneg vneg vneg vpos vpos vpos vpos AA on2 op2 on0 op0 vpos vpos vpos AB op3 on1 op1 vpos vpos vpos vpos AC 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 5. BGA Bottom View Pinout Rev. PrA | Page 8 of 32 Preliminary Technical Data AD8117/AD8118 1 vpos A vpos B vpos C vpos D ip1 E in1 F ip3 G in3 H ip5 J in5 K ip7 L in7 M ip9 N in9 P ip11 R in11 T ip13 U in13 V ip15 W in15 Y vpos AA vpos AB vpos AC 2 vpos 3 vpos 4 on31 5 op31 6 on29 7 op29 8 on27 9 op27 10 on25 11 op25 12 on23 13 op23 14 on21 15 op21 16 on19 17 op19 18 on17 19 op17 20 vpos 21 vpos 22 vpos 23 vpos A vpos vpos vpos on30 op30 on28 op28 on26 op26 on24 op24 on22 op22 on20 op20 on18 op18 on16 op16 vpos vpos vpos B vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos C ip0 vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vocm vneg vpos vpos in16 D in0 vneg vocm vocm vneg in17 ip16 E ip2 vneg vdd vdd vneg ip17 in18 F in2 vneg dgnd dgnd vneg in19 ip18 G ip4 vneg data_out resetb vneg ip19 in20 H in4 vneg clk updateb vneg in21 ip20 J ip6 vneg data_in web vneg ip21 in22 K in6 vpos serbpar PRELIMINARY d5 vpos in23 ip22 L ip8 vpos a4 Top View PRELIMINARY d4 vpos ip23 in24 M in8 vpos a3 d3 vpos in25 ip24 N ip10 vneg a2 d2 vneg ip25 in26 P in10 vneg a1 d1 vneg in27 ip26 R ip12 vneg a0 d0 vneg ip27 in28 T in12 vneg vdd vdd vneg in29 ip28 U ip14 vneg dgnd dgnd vneg ip29 in30 V in14 vneg vocm vocm vneg in31 ip30 W vpos vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vocm vneg vpos ip31 vpos Y vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos AA vpos vpos op0 on0 op2 on2 op4 on4 op6 on6 op8 on8 op10 on10 op12 on12 op14 on14 vpos vpos vpos vpos AB vpos vpos vpos op1 on1 op3 on3 op5 on5 op7 on7 op9 on9 op11 on11 op13 on13 op15 on15 vpos vpos vpos AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Figure 6. BGA Top View Pinout Table 6. Ball Grid Description Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Mnemonic VPOS VPOS VPOS ON31 OP31 ON29 OP29 ON27 OP27 ON25 OP25 ON23 Description Analog positive power supply. Analog positive power supply. Analog positive power supply. Output number 31, negative phase. Output number 31, positive phase. Output number 29, negative phase. Output number 29, positive phase. Output number 27, negative phase. Output number 27, positive phase. Output number 25, negative phase. Output number 25, positive phase. Output number 23, negative phase. Ball A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 Rev. PrA | Page 9 of 32 Mnemonic OP23 ON21 OP21 ON19 OP19 ON17 OP17 VPOS VPOS VPOS VPOS VPOS Description Output number 23, positive phase. Output number 21, negative phase. Output number 21, positive phase. Output number 19, negative phase. Output number 19, positive phase. Output number 17, negative phase. Output number 17, positive phase. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. AD8117/AD8118 Ball B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 Mnemonic VPOS VPOS VPOS ON30 OP30 ON28 OP28 ON26 OP26 ON24 OP24 ON22 OP22 ON20 OP20 ON18 OP18 ON16 OP16 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS IP0 VPOS VNEG VOCM Description Analog positive power supply. Analog positive power supply. Analog positive power supply. Output number 30, negative phase. Output number 30, positive phase. Output number 28, negative phase. Output number 28, positive phase. Output number 26, negative phase. Output number 26, positive phase. Output number 24, negative phase. Output number 24, positive phase. Output number 22, negative phase. Output number 22, positive phase. Output number 20, negative phase. Output number 20, positive phase. Output number 18, negative phase. Output number 18, positive phase. Output number 16, negative phase. Output number 16, positive phase. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Input number 0, positive phase. Analog positive power supply. Analog negative power supply. Output common-mode reference supply. Ball D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 G4 G20 G21 G22 G23 H1 H2 H3 H4 H20 H21 H22 H23 Mnemonic VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VOCM VNEG VPOS VPOS IN16 IP1 IN0 VNEG VOCM VOCM VNEG IN17 IP16 IN1 IP2 VNEG VDD VDD VNEG IP17 IN18 IP3 IN2 VNEG DGND DGND VNEG IN19 IP18 IN3 IP4 VNEG DATA_OUT RESETB VNEG IP19 IN20 Preliminary Technical Data Description Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Output common-mode reference supply. Analog negative power supply. Analog positive power supply. Analog positive power supply. Input number 16, negative phase. Input number 1, positive phase. Input number 0, negative phase. Analog negative power supply. Output common-mode reference supply. Output common-mode reference supply. Analog negative power supply. Input number 17, negative phase. Input number 16, positive phase. Input number 1, negative phase. Input number 2, positive phase. Analog negative power supply. Logic positive power supply. Logic positive power supply. Analog negative power supply. Input number 17, positive phase. Input number 18, negative phase. Input number 3, positive phase. Input number 2, negative phase. Analog negative power supply. Logic negative power supply. Logic negative power supply. Analog negative power supply. Input number 19, negative phase. Input number 18, positive phase. Input number 3, negative phase. Input number 4, positive phase. Analog negative power supply. Control pin: serial data out. Control pin: second rank data reset. Analog negative power supply. Input number 19, positive phase. Input number 20, negative phase. Rev. PrA | Page 10 of 32 Preliminary Technical Data Ball J1 J2 J3 J4 J20 J21 J22 J23 K1 K2 K3 K4 K20 K21 K22 K23 L1 L2 L3 L4 L20 L21 L22 L23 M1 M2 M3 M4 M20 M21 M22 M23 N1 N2 N3 N4 N20 N21 N22 N23 P1 P2 P3 P4 P20 P21 P22 P23 R1 R2 Mnemonic IP5 IN4 VNEG CLK UPDATEB VNEG IN21 IP20 IN5 IP6 VNEG DATA_IN WEB VNEG IP21 IN22 IP7 IN6 VPOS SERBPAR D5 VPOS IN23 IP22 IN7 IP8 VPOS A4 D4 VPOS IP23 IN24 IP9 IN8 VPOS A3 D3 VPOS IN25 IP24 IN9 IP10 VNEG A2 D2 VNEG IP25 IN26 IP11 IN10 Description Input number 5, positive phase. Input number 4, negative phase. Analog negative power supply. Control pin: serial data clock. Control pin: second rank write strobe. Analog negative power supply. Input number 21, negative phase. Input number 20, positive phase. Input number 5, negative phase. Input number 6, positive phase. Analog negative power supply. Control pin: serial data in. Control pin: first rank write strobe. Analog negative power supply. Input number 21, positive phase. Input number 22, negative phase. Input number 7, positive phase. Input number 6, negative phase. Analog positive power supply. Control pin: serial/parallel mode select. Control pin: input address bit 5. Analog positive power supply. Input number 23, negative phase. Input number 22, positive phase. Input number 7, negative phase. Input number 8, positive phase. Analog positive power supply. Control pin: output address bit 4. Control pin: input address bit 4. Analog positive power supply. Input number 23, positive phase. Input number 24, negative phase. Input number 9, positive phase. Input number 8, negative phase. Analog positive power supply. Control pin: output address bit 3. Control pin: input address bit 3. Analog positive power supply. Input number 25, negative phase. Input number 24, positive phase. Input number 9, negative phase. Input number 10, positive phase. Analog negative power supply. Control pin: output address bit 2. Control pin: input address bit 2. Analog negative power supply. Input number 25, positive phase. Input number 26, negative phase. Input number 11, positive phase. Input number 10, negative phase. Ball R3 R4 R20 R21 R22 R23 T1 T2 T3 T4 T20 T21 T22 T23 U1 U2 U3 U4 U20 U21 U22 U23 V1 V2 V3 V4 V20 V21 V22 V23 W1 W2 W3 W4 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Mnemonic VNEG A1 D1 VNEG IN27 IP26 IN11 IP12 VNEG A0 D0 VNEG IP27 IN28 IP13 IN12 VNEG VDD VDD VNEG IN29 IP28 IN13 IP14 VNEG DGND DGND VNEG IP29 IN30 IP15 IN14 VNEG VOCM VOCM VNEG IN31 IP30 IN15 VPOS VPOS VNEG VOCM VNEG VNEG VNEG VNEG VNEG VPOS VPOS AD8117/AD8118 Description Analog negative power supply. Control pin: output address bit 1. Control pin: input address bit 1. Analog negative power supply. Input number 27, negative phase. Input number 26, positive phase. Input number 11, negative phase. Input number 12, positive phase. Analog negative power supply. Control pin: output address bit 0. Control pin: input address bit 0. Analog negative power supply. Input number 27, positive phase. Input number 28, negative phase. Input number 13, positive phase. Input number 12, negative phase. Analog negative power supply. Logic positive power supply. Logic positive power supply. Analog negative power supply. Input number 29, negative phase. Input number 28, positive phase. Input number 13, negative phase. Input number 14, positive phase. Analog negative power supply. Logic negative power supply. Logic negative power supply. Analog negative power supply. Input number 29, positive phase. Input number 30, negative phase. Input number 15, positive phase. Input number 14, negative phase. Analog negative power supply. Output common-mode reference supply. Output common-mode reference supply. Analog negative power supply. Input number 31, negative phase. Input number 30, positive phase. Input number 15, negative phase. Analog positive power supply. Analog positive power supply. Analog negative power supply. Output common-mode reference supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog positive power supply. Analog positive power supply. Rev. PrA | Page 11 of 32 AD8117/AD8118 Ball Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 Mnemonic VPOS VNEG VNEG VNEG VNEG VNEG VOCM VNEG VPOS IP31 VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS VPOS VPOS OP0 ON0 OP2 Description Analog positive power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Output common-mode reference supply. Analog negative power supply. Analog positive power supply. Input number 31, positive phase. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog negative power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Output number 0, positive phase. Output number 0, negative phase. Output number 2, positive phase. Ball AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Mnemonic ON2 OP4 ON4 OP6 ON6 OP8 ON8 OP10 ON10 OP12 ON12 OP14 ON14 VPOS VPOS VPOS VPOS VPOS VPOS VPOS VPOS OP1 ON1 OP3 ON3 OP5 ON5 OP7 ON7 OP9 ON9 OP11 ON11 OP13 ON13 OP15 ON15 VPOS VPOS VPOS Preliminary Technical Data Description Output number 2, negative phase. Output number 4, positive phase. Output number 4, negative phase. Output number 6, positive phase. Output number 6, negative phase. Output number 8, positive phase. Output number 8, negative phase. Output number 10, positive phase. Output number 10, negative phase. Output number 12, positive phase. Output number 12, negative phase. Output number 14, positive phase. Output number 14, negative phase. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Analog positive power supply. Output number 1, positive phase. Output number 1, negative phase. Output number 3, positive phase. Output number 3, negative phase. Output number 5, positive phase. Output number 5, negative phase. Output number 7, positive phase. Output number 7, negative phase. Output number 9, positive phase. Output number 9, negative phase. Output number 11, positive phase. Output number 11, negative phase. Output number 13, positive phase. Output number 13, negative phase. Output number 15, positive phase. Output number 15, negative phase. Analog positive power supply. Analog positive power supply. Analog positive power supply. Rev. PrA | Page 12 of 32 Preliminary Technical Data Table 7. Operation Truth Table UPDATE X X X X X X CLK X X X X X X DATA IN X X X X X X DATA OUT X X X X X X WE X X X X X X RESET 0 1 1 1 1 1 SER/PAR X X X X X X AD8117/AD8118 Operation/Comment Asynchronous reset. All outputs are disabled. tbd tbd tbd tbd tbd Figure 7. Logic Diagram Rev. PrA | Page 13 of 32 AD8117/AD8118 Preliminary Technical Data OPn IPn 2500 1.3pF 0.3pF 2538 3.4pF OPn,ONn 0.4pF 30k 3.4pF INn 1.3pF 2500 2538 ONn a. AD8117/AD8118 Enabled Output (see also ESD Protection Map) b. AD8117/AD8118 Disabled Output (see also ESD Protection Map) c. AD8117 Receiver (see also ESD Protection Map) IPn 2500 1.3pF 0.3pF 1.3pF 5075 IPn 1.3pF 0.3pF 1.3pF 2500 2500 IPn 3.33k AD8117 G=+1 3.76k AD8118 G=+2 1.6pF INn 2500 5075 INn INn d. AD8118 Receiver (see also ESD Protection Map) e. AD8117/AD8118 Receiver Simplified Equivalent Circuit When Driving Differentially f. AD8117/AD8118 Receiver Simplified Equivalent Circuit When Driving Single-Ended VDD 25k RESET 1k VOCM CLK, SER/PAR, WE, UPDATE, DATA IN, A[4:0], D[4:0] 1k VNEG DGND DGND g. VOCM input (see also ESD Protection Map) VDD h. Reset Input (see also ESD Protection Map) VPOS VDD CLK, RESET, SER/PAR, WE, UPDATE, DATA IN, DATA OUT, A[4:0], D[5:0] VNEG DGND i. Logic Input (see also ESD Protection Map) DATA OUT IPn, INn, OPn, ONn, VOCM DGND j. Logic Output (see also ESD Protection Map) k. ESD Protection Map Figure 8. I/O Schematics Rev. PrA | Page 14 of 32 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 4 2 0 CROSSTALK (dB) AD8117/AD8118 0 VOUT = 1 VPP Single-ended -20 Differential In/Out -2 GAIN (dB) -4 -6 -8 -10 -12 -14 -16 300 k 1M 10 M 100 M FREQUENCY (Hz) 1G 8G -40 -60 -80 -100 300 k 1M 10 M 100 M FREQUENCY (Hz) 1G 2G Figure 9. AD8117 Large Signal Frequency Response Figure 12. AD8117 Crosstalk, One Adjacent Channel, Differential Mode 0 Differential In/Out -10 0 Single-Ended In/Out -20 CROSSTALK (dB) -20 CMRR (dB) -30 -40 -50 -40 -60 -80 -60 -70 300 k -100 300 k 1M 10 M 100 M FREQUENCY (Hz) 1G 2G 1M 10 M 100 M FREQUENCY (Hz) 1G 2G Figure 10. AD8117 Common-Mode Rejection Figure 13. AD8117 Crosstalk, One Adjacent Channel, Single-Ended Mode 140 NOISE SPECTRAL DENSITY (nV/rtHz) 0 Differential Out 120 100 80 60 40 -80 -20 CROSSTALK (dB) Differential In/Out -40 -60 20 0 1k -100 300 k 10 k 100 k FREQUENCY (Hz) 1M 1M 10 M 100 M FREQUENCY (Hz) 1G 2G Figure 11. AD8117 Noise Spectral Density, Differential Mode Figure 14. AD8117 Crosstalk, All-Hostile, Differential Mode Rev. PrA | Page 15 of 32 AD8117/AD8118 0 Single-Ended In/Out Preliminary Technical Data 5k Differential In INPUT IMPEDANCE (Ohms) -20 CROSSTALK (dB) 4k -40 3k -60 2k -80 1k -100 300 k 1M 10 M 100 M FREQUENCY (Hz) 1G 2G 0 300 k 1M 10 M FREQUENCY (Hz) 100 M 1G Figure 15. AD8117 Crosstalk, All-Hostile, Single-Ended Mode Figure 18. AD8117 Input Impedance, Differential Mode 0 Differential In/Out -20 CROSSTALK (dB) 3.5k Single-Ended In 3.0k INPUT IMPEDANCE (Ohms) 1M 10 M 100 M FREQUENCY (Hz) 1G 2G 2.5k 2.0k 1.5k 1.0k 0.5k -40 -60 -80 -100 300 k 0 300 k 1M 10 M FREQUENCY (Hz) 100 M 1G Figure 16. AD8117 Crosstalk, Off-Isolation, Differential Mode Figure 19. AD8117 Input Impedance, Single-Ended Mode 0 Single-Ended In/Out 30k Differential Out OUTPUT IMPEDANCE (Ohms) 1M 10 M 100 M FREQUENCY (Hz) 1G 2G -20 CROSSTALK (dB) 25k 20k -40 15k -60 10k -80 5k -100 300 k 0 100 k 1M 10 M FREQUENCY (Hz) 100 M 1G Figure 17. AD8117 Crosstalk, Off-Isolation, Single-Ended Mode Figure 20. AD8117 Output Impedance, Disabled, Differential Mode Rev. PrA | Page 16 of 32 Preliminary Technical Data 25k Single-Ended Out OUTPUT IMPEDANCE (Ohms) AD8117/AD8118 20k 15k 10k 5k 0 300 k 1M 10 M FREQUENCY (Hz) 100 M 1G Figure 21. AD8117 Output Impedance, Disabled, Single-Ended Mode Rev. PrA | Page 17 of 32 AD8117/AD8118 THEORY OF OPERATION The AD8117 is a fully-differential crosspoint array with 32 outputs, each of which can be connected to any one of 32 inputs. Organized by output row, 32 switchable input transconductance stages are connected to each output buffer to form 32-to-1 multiplexers. There are 32 of these multiplexers, each with its inputs wired in parallel, for a total array of 1,024 transconductance stages forming a multicast-capable crosspoint switch. Decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. The enabled transconductance stage drives the output stage, and feedback forms a closed-loop amplifier with a differential gain of one (the difference between the output voltages is equal to the difference between the input voltages). A second feedback loop controls the common-mode output level, forcing the average of the differential output voltages to match the voltage on the VOCM reference pin. Although each output has an independent common-mode control loop, the VOCM reference is common for the entire chip, and as such needs to be driven with a low impedance to avoid crosstalk. Each differential input to the AD8117 is buffered by a receiver. The purpose of this receiver is to provide an extended input common-mode range, and to remove this common-mode from the signal chain. Like the output multiplexers, the input receiver has both a differential loop and a common-mode control loop. A mask-programmable feedback network sets the closed-loop differential gain. For the AD8117, this differential gain is one, and for the AD8118, this is a differential gain of two. The receiver has an input stage that does not respond to the common-mode of the signal. This architecture, along with the attenuating feedback network, allows the user to apply input voltages that extend from rail-to-rail. Excess differential loop gain-bandwidth product reduces the effect of the closed-loop gain on the bandwidth of the device. The output stage of the AD8117 is designed for low differential gain and phase error when driving composite video signals. It also provides slew current for fast pulse response when driving component video signals. Unlike many multiplexer designs, these requirements are balanced such that large signal bandwidth is very similar to small signal bandwidth. The design load is 150 , but provisions are made to drive loads as low as 75 so long as on-chip power dissipation limits are not exceeded. The outputs of the AD8117 can be disabled to minimize onchip power dissipation. When disabled, there is only a common-mode feedback network of 30k between the Preliminary Technical Data differential outputs. This high impedance allows multiple ICs to be bussed together without additional buffering. Care must be taken to reduce output capacitance, which will result in more overshoot and frequency-domain peaking. A series of internal amplifiers drive internal nodes such that a wide-band highimpedance is presented at the disabled output, even while the output bus is under large signal swings. When the outputs are disabled and driven externally, the voltage applied to them should not exceed the valid output swing range for the AD8117 in order to keep these internal amplifiers in their linear range of operation. Applying excess differential voltages to the disabled outputs can cause damage to the AD8117 and should be avoided (see the Absolute Maximum Ratings section of this datasheet for guidelines). The connection of the AD8117 is controlled by a flexible TTL compatible logic interface. Either parallel or serial loading into a first rank of latches preprograms each output. A global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. In serial mode, a serial-out pin allows devices to be daisy chained together for single-pin programming of multiple ICs. A poweron reset pin is available to avoid bus conflicts by disabling all outputs. This power-on reset clears the second rank of latches, but does not clear the first rank of latches. In parallel mode, to quickly clear the first rank, a broadcast parallel programming feature is available. In serial-mode, pre-programming individual inputs is not possible and the entire shift register needs to be flushed. The AD8117 can operate on a single +5 V supply, powering both the signal path (with the VPOS/VNEG supply pins), and the control logic interface (with the VDD/DGND supply pins). But in order to easily interface to ground-referenced video signals, split supply operation is possible with 2.5 V supplies. In this case, a flexible logic interface allows the control logic supplies (VDD/DGND) to be run off +2 V/0 V to +3.3 V/0 V while the core remains on split supplies. Additional flexibility in the analog output common-mode level facilitates unequal split supplies. If +3 V/-2 V supplies to +2 V/-3 V supplies are desired, the VOCM pin can still be set to 0 V for groundreferenced video signals. Rev. PrA | Page 18 of 32 Preliminary Technical Data APPLICATIONS PROGRAMMING The AD8117/AD8118 have two options for changing the programming of the crosspoint matrix. In the first option a serial word of 192 bits can be provided that will update the entire matrix each time. The second option allows for changing a single output's programming via a parallel interface. The serial option requires fewer signals, but more time (clock cycles) for changing the programming, while the parallel programming technique requires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming. AD8117/AD8118 sequence will be 192 bits times the number of devices in the chain. Parallel Programming Description When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output at a time. Since this takes only one WE/UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RESET signal does not reset all registers in the AD8117. When taken LOW, the RESET signal will only set each output to the disabled state. This is helpful during powerup to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device will generally have random data, even though the RESET signal has been asserted. If parallel programming is used to program one output, then that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up. This will ensure that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single output or more at a time. In similar fashion, if UPDATE is taken LOW after initial power-up, the random power-up data in the shift register will be programmed into the matrix. Therefore, in order to prevent the crosspoint from being programmed into an unknown state, do not apply a low logic level to UPDATE after power is initially applied. Programming the full shift register one time to a desired state, by either serial or parallel programming after initial power-up, will eliminate the possibility of programming the matrix to an unknown state. To change an output's programming via parallel programming, SER/PAR and UPDATE should be taken HIGH. The serial programming clock, CLK, should be left HIGH during parallel programming. The parallel clock, WE, should start in the HIGH state. The 5-bit address of the output to be programmed should be put on A0-A4. The first five data bits (D0-D4) should contain the information that identifies the input that gets programmed to the output that is addressed. The sixth data bit (D5) will determine the enabled state of the output. If D5 is LOW (output disabled), then the data on D0-D4 does not matter. Serial Programming Description The serial programming mode uses the device pins CLK, DATA IN, UPDATE and SER/PAR. The first step is to assert a LOW on SER/PAR in order to enable the serial programming mode. The parallel clock, WE should be held HIGH during the entire serial programming operation. The UPDATE signal should be high during the time that data is shifted into the device's serial port. Although the data will still shift in when UPDATE is LOW, the transparent, asynchronous latches will allow the shifting data to reach the matrix. This will cause the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every falling edge of CLK. A total of 192 bits must be shifted in to complete the programming. For each of the 32 outputs, there are five bits (D0-D4) that determine the source of its input followed by one bit (D5) that determines the enabled state of the output. If D5 is LOW (output disabled), the four associated bits (D0-D4) do not matter, because no input will be switched to that output. The most-significant-output-address data is shifted in first, then following in sequence until the least-significant-outputaddress data is shifted in. At this point UPDATE can be taken low, which will cause the programming of the device according to the data that was just shifted in. The UPDATE latches are asynchronous and when UPDATE is low they are transparent. If more than one AD8117 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, UPDATE, and SER/PAR pins should be connected in parallel and operated as described above. The serial data is input to the DATA IN pin of the first device of the chain, and it will ripple through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming Rev. PrA | Page 19 of 32 AD8117/AD8118 After the desired address and data signals have been established, they can be latched into the shift register by a high to low transition of the WE signal. The matrix will not be programmed, however, until the UPDATE signal is taken low. It is thus possible to latch in new data for several or all of the outputs first via successive negative transitions of WE while UPDATE is held HIGH, and then have all the new data take effect when UPDATE goes LOW. This is the technique that should be used when programming the device for the first time after power-up when using parallel programming. Preliminary Technical Data fashion. This presents several options for circuit configurations that will require different gains and treatment of terminations, if they are used. Differential Input The AD8117/AD8118 has differential input receivers. These receivers allow the user to drive the inputs with a differential signal with an uncertain common-mode voltage, such as from a remote source over twisted pair. The receivers will respond only to the difference in input voltages, and will restore a common-mode voltage suitable for the internal signal path. Noise or crosstalk that is present in both inputs will be rejected by the input stage, as specified by its common-mode rejection ratio (CMRR). Differential operation offers a great noise benefit for signals that are propagated over distance in a noisy environment. RF RG Reset When powering up the AD8117, it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken LOW, will cause all outputs to be in the disabled state. However, the RESET signal does not reset all registers in the AD8117. This is important when operating in the parallel programming mode. Please refer to that section for information about programming internal registers after powerup. Serial programming will program the entire matrix each time, so no special considerations apply. Since the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. To prevent this, do not apply a logic low signal to UPDATE initially after power-up. The shift register should first be loaded with the desired data, and then UPDATE can be taken LOW to program the device. The RESET pin has a 20 k pull-up resistor to VDD that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground will hold RESET low for some time while the rest of the device stabilizes. The low condition will cause all the outputs to be disabled. The capacitor will then charge through the pull-up resistor to the high state, thus allowing full programming capability of the device. IN+ VOCM IN- OUT- RCVR RG to switch matrix OUT+ RF Figure 22. Input Receiver Equivalent Circuit The circuit configuration used by the differential input receivers is similar to that of several Analog Devices general-purpose differential amplifiers, such as the AD8131. It is a voltagefeedback amplifier with internal gain setting resistors. The arrangement of feedback makes the differential input impedance appear to be 5 k across the inputs. RIN, dm = 2 x RG = 5 k This impedance will create a small differential termination error if the user does not account for the 5 k parallel element, although this error will be less than 1% in most cases. Additionally, the source impedance driving the AD8117 appears in parallel with the internal gain-setting resistors, such that there may be a gain error for some values of source resistance. The AD8117/AD8118 are adjusted such that their gains will be correct when driven by a back-terminated 75 source impedance at each input phase (37.5 effective impedance to ground at each input pin, or 75 differential source impedance across pairs of input pins). If a different source impedance is presented, the differential gain of the AD8117/AD8118 can be calculated by VOUT, dm VIN, dm RF RG + RS Broadcast The AD8117 logic interface has a broadcast mode, in which all first rank latches can be simultaneously parallel-programmed to the same data in one write-cycle. This is especially useful in clearing random first rank data after power-up. To access the broadcast mode, the part is parallel-programmed using the device pins WE, A0-A4, D0-A5 and UPDATE. The only difference is that the SER/PAR pin is held LOW, as if serial programming. By holding CLK high, no serial clocking will occur, and instead the WE can be used to clock all first rank latches in the chip at once. OPERATING MODES The AD8117/AD8118 has fully-differential inputs and outputs. The inputs and outputs can also be operated in a single-ended Gdm = = Rev. PrA | Page 20 of 32 Preliminary Technical Data where RG is 2.5 k , RS is the user single-ended source resistance (such as 37.5 for a back-terminated 75 source), and RF is 2.538 k for the AD8117 and 5.075 k for the AD8118. In the case of the AD8117, this is 2.538 k 2.5 k + RS AD8117/AD8118 the AD8117/AD8118 will create a high-pass filter with the input impedance of the device. This capacitor will need to be sized such that the corner frequency is low enough for frequencies of interest. Single-ended Input Gdm = The AD8117/AD8118 input receiver can also be driven singleended (unbalanced). From the standpoint of the receiver, there is very little difference between signals applied positive and negative in two phases to the input pair, versus a signal applied to one input only with the other input held at a constant potential. One small difference is that the common-mode between the input pins will be changing if only one input is moving, and there is a very small common-mode to differential conversion gain in the receiver that will add an additional gain error to the output (see the common-mode rejection ratio specifications for the input stage). For low frequencies, this gain error is negligible. The common-mode rejection ratio degrades with increasing frequency. When operating the AD8117/AD8118 receiver single-endedly, the observed input resistance at each input pin is higher than in the differential input case, due to a fraction of the receiver internal output voltage appearing as a common-mode signal on its input terminals, bootstrapping the voltage on the input resistance. This single-ended input resistance can be calculated by the formula RG + RS 1- RF 2 x (RG + RS + RF) + RF In the case of the AD8118, this is 5.075 k 2.5 k + RS Gdm = When operating with a differential input, care must be taken to keep the common-mode, or average, of the input voltages within the linear operating range of the AD8117/AD8118 receiver. This common-mode range can extend rail-to-rail, provided the differential signal swing is small enough to avoid forward biasing the ESD diodes (it is safest to keep the common-mode plus differential signal excursions within the supply voltages of the part). The differential output of the AD8117/AD8118 receiver is linear for a peak of 1.4V of output voltage difference (1.4 V peak input difference for the AD8117, and 0.7 V peak input difference for the AD8118). Taking the output differentially, using the two output phases, this allows 2.8 VPP of linear output signal swing. Beyond this level, the signal path will saturate and limit the signal swing. This is not a desired operation, as the supply current will increase and the signal path will be slow to recover from clipping. The absolute maximum allowed differential input signal is limited by long-term reliability of the input stage. The limits in the Absolute Maximum Ratings section of the datasheet should be observed in order to avoid degrading device performance permanently. AD8117 IPn INn 50 50 RCVR OPn ONn RIN = where RG is 2.5 k , RS is the user single-ended source resistance (such as 37.5 for a back-terminated 75 source), and RF is 2.538 k for the AD8117 and 5.075 k for the AD8118. In most cases, a single-ended input signal will be referred to mid-supply, typically ground. In this case, the undriven differential input could be connected to ground. For best dynamic performance and lowest offset voltage, this unused input should be terminated with an impedance matching the driven input, instead of being directly shorted to ground. Due to the differential feedback of the receiver, there is highfrequency signal current in the undriven input and it should be treated as a signal line in the board design. Figure 23. Example of Input Driven Differentially AC-Coupling It is possible to AC-couple the inputs of the AD8117/AD8118 receiver. This is simplified in that bias current does not need to be supplied externally. A capacitor in series with the inputs to Rev. PrA | Page 21 of 32 AD8117/AD8118 AD8117 IPn INn 75 75 (or 37.5) RCVR OPn ONn Preliminary Technical Data The VOCM reference is a high-speed signal input, common to all output stages on the device. It requires only small amounts of bias current, but noise appearing on this pin will be buffered to the outputs of all the output stages. As such, the VOCM node should be connected to a low-noise, low-impedance voltage to avoid being a source of noise, offset and crosstalk in the signal path. Termination The AD8117/AD8118 is designed to drive 150 on each output (or an effective 300 differential) while meeting datasheet specifications, but the output stage is capable of supplying the current to drive 100 loads (200 differential) over the specified operating temperature range. If care is taken to observe the maximum power derating curves, the output stage can drive 75 loads with slightly reduced slew rate and bandwidth (an effective 150 differential load). Termination at the load end is recommended for best signal integrity. This load termination is often a resistor to a ground reference on each individual output. By terminating to the same voltage level that drives the VOCM reference, the power dissipation due to DC termination current will be reduced. In differential signal paths, it is often desirable to terminate differentially, with a single resistor across the differential outputs at the load end. This is acceptable for the AD8117/AD8118, but when the device outputs are placed in a disabled state, a small amount of DC bias current is required if the output is to present as a high-impedance over an excursion of output bus voltages. If the AD8117/AD8118 disabled outputs are floated (or simply tied together by a resistor), internal nodes will saturate and an increase in disabled output current may be observed. For best pulse response, it is often desirable to place a series resistor in each output to match the characteristic impedance and termination of the output trace or cable. This is known as back-termination, and helps shorten settling time by terminating reflected signals when driving a load that is not accurately terminated at the load end. A side-effect of backtermination is an attenuation of the output signal by a factor of two. In this case, a gain of two is usually necessary somewhere in the signal path to restore the signal. AD8117 Figure 24. Example of Input Driven Single-Ended Differential Output Benefits of Differential Operation The AD8117/AD8118 has a fully-differential switch core, with differential outputs. The two output voltages move in opposite directions, with a differential feedback loop maintaining a fixed output stage differential gain of +1 (the different overall signal path gains between the AD8117 and AD8118 are set in the input stage for best signal-to-noise ratio). This differential output stage provides a benefit of crosstalk-canceling due to parasitic coupling from one output to another being equal and out of phase. Additionally, if the output of the device is utilized in a differential design, noise, crosstalk and offset voltages generated on-chip that are coupled equally into both outputs will be cancelled by the common-mode rejection ratio of the next device in the signal chain. By utilizing the AD8117/AD8118 outputs in a differential application, the best possible noise and offset specifications can be realized. Differential Gain The specified signal path gain of the AD8117/AD8118 refers to its differential gain. For the AD8117, the gain of +1 means that the difference in voltage between the two output terminals is equal to the difference applied between the two input terminals. For the AD8118, the ratio of output difference voltage to applied input difference voltage is +2. The common-mode, or average voltage of the pair of output signals is set by the voltage on the VOCM pin. This voltage is typically set to mid-supply (often ground), but may be moved approximately 0.5 V in order to accommodate cases where the desired output common-mode voltage may not be midsupply (as in the case of unequal split supplies). Adjusting VOCM beyond 0.5 V can limit differential swing internally below the specifications on the datasheet. Regardless of the differential gain of the device, the commonmode gain for the AD8117 and AD8118 is +1 to the output. This means that the common-mode of the output voltages will directly follow the reference voltage applied to the VOCM input. OPn ONn 50 100 50 Rev. PrA | Page 22 of 32 Preliminary Technical Data Figure 25. Example of Back-Terminated Differential Load AD8117/AD8118 observed. An AD8117 taken with single-ended output will appear to have a gain of +0.5. An AD8118 will be a singleended gain of +1. This factor of one-half in the gain increases the noise of the device when referred to the input, contributing to higher noise specifications for single-ended output designs. Termination When operating the AD8117/AD8118 with a single-ended output, the preferred output termination scheme is a resistor at the load end to the VOCM voltage. A back-termination may be used, at an additional cost of one half the signal gain. In single-ended output operation, the second phase of the output is not used, and may or may not be terminated locally. Termination of the unused output is not necessary for proper device operation, so total design power dissipation can be reduced by floating this output. However, there are several reasons for terminating the unused output with a load resistance equal to the signal output. One component of crosstalk is magnetic, coupling by mutual inductance between output package traces and bond wires that carry load current. In a differential design, there is coupling from one pair of outputs to other adjacent pairs of outputs. The differential nature of the output signal simultaneously drives the coupling field in one direction for one phase of the output, and in an opposite direction for the other phase of the output. These magnetic fields do not couple exactly equal into adjacent output pairs due to different proximities, but they do destructively cancel the crosstalk to some extent. If the load current in each output is equal, this cancellation will be greater and less adjacent crosstalk will be observed (regardless if the second output is actually being used). A second benefit of balancing the output loads in a differential pair is to reduce fluctuations in current requirements from the power supply. In single-ended loads, the load currents alternate from the positive supply to the negative supply. This creates a parasitic signal voltage in the supply pins due to the finite resistance and inductance of the supplies. This supply fluctuation appears as crosstalk in all outputs, attenuated by the power supply rejection ratio (PSRR) of the device. At low frequencies, this is a negligible component of crosstalk, but PSRR falls off as frequency increases. With differential, balanced loads, as one output draws current from the positive supply, the other output draws current from the negative supply. When the phase alternates, the first output draws current from the negative supply and the second from the positive supply. The effect is that a more constant current is drawn from each supply, such that the crosstalk-inducing supply fluctuation is minimized. Single-ended Output Usage The AD8117/AD8118 output pairs can be used single-endedly, taking only one output and not using the second. This is often desired to reduce the routing complexity in the design, or because a single-ended load is being driven directly. This mode of operation will produce good results, but has some shortcomings when compared to taking the output differentially. When observing the single-ended output, noise that is common to both outputs appears in the output signal. This includes thermal noise in the chip biasing, as well as crosstalk that coupled into the signal path. This component noise and crosstalk is equal in both outputs, and as such can be ignored by a differential receiver with high common-mode rejection ratio. But when taking the output single-ended, this noise is present with respect to the ground (or VOCM) reference and is not rejected. When observing the output single-ended, the distribution of offset voltages will appear greater. In the differential case, the difference between the outputs when the difference between the inputs is zero will be a small differential offset. This offset of created from mismatches in components of the signal path which must be corrected by the finite differential loop gain of the device. In the single-ended case, this differential offset is still observed, but an additional offset component is also relevant. This additional component is the common-mode offset, which is a difference between the average of the outputs and the VOCM reference. This offset is created by mismatches that affect the signal path in a common-mode manner, and is corrected by the finite common-mode loop gain of the device. A differential receiver would reject this common-mode offset voltage, but in the single ended case this offset is observed with respect to the signal ground. The single-ended output sums half the differential offset voltage and all of the common-mode offset voltage for a net gain in observed random offset. Single-Ended Gain The AD8117/AD8118 operates as a closed-loop differential amplifier. The primary control loop forces the difference between the output terminals to be a ratio of the difference between the input terminals. One output will increase in voltage, while the other decreases an equal amount to make the total difference correct. The average of these output voltages is forced to the voltage on the VOCM terminal by a second control loop. If only one output terminal is observed with respect to the VOCM terminal, only half of the difference voltage will be observed. This implies that when using only one output of the device, half of the differential gain will be Rev. PrA | Page 23 of 32 AD8117/AD8118 A third benefit of driving balanced loads can be seen if one considers that the output pulse response will change as load changes. The differential signal control loop in the AD8117/AD8118 forces the difference of the outputs to be a fixed ratio to the difference of the inputs. If the two output responses are different due to loading, this creates a difference that the control loop will see as signal response error, and it will attempt to correct this error. This will distort the output signal from the ideal response if the two outputs were balanced. AD8117 Preliminary Technical Data operation as there is a common-mode to differential gain conversion that becomes greater at higher frequencies. During operation of the AD8117/AD8118, transient currents will flow into the VOCM net from the amplifier control loops. Although the magnitude of these currents are small (10 - 20 A per output), they can contribute to crosstalk if they flow through significant impedances. Driving VOCM with a lowimpedance, low-noise source is desirable. Power Dissipation OPn ONn 75 150 75 Calculation of Power Dissipation 8.0 TJ = 150 C Figure 26. Example of Back-Terminated Single-Ended Load MAXIMUM POWER - Watts 7.0 6.0 Decoupling The signal path of the AD8117/AD8118 is based on high open loop gain amplifiers with negative feedback. Dominant-pole compensation is used on-chip to stabilize these amplifiers over the range of expected applied swing and load conditions. To guarantee this designed stability, proper supply decoupling is necessary with respect to both the differential control loops and the common-mode control loops of the signal path. Signalgenerated currents must return to their sources through lowimpedance paths at all frequencies in which there is still loop gain (up to 700 MHz at a minimum). Refer to the example Evaluation Board schematic as an example of wideband parallel capacitor arrangements that can properly decouple the AD8117/AD8118. The signal path compensation capacitors in the AD8117/AD8118 are connected to the VNEG supply. At high frequencies, this limits the power supply rejection ratio (PSRR) from the VNEG supply to a lower value than that from the VPOS supply. If given a choice, an application board should be designed such that the VNEG power is supplied from a lowinductance plane, subject to a least amount of noise. The VOCM should be considered a reference pin and not a power supply. It is an input to the high-speed, high-gain common-mode control loop of all receivers and output drivers. In the single-ended output sense, there is no rejection from noise on the VOCM net to the output. For this reason, care must be taken to produce a low-noise VOCM source over the entire range of frequencies of interest. This is not only important to single-ended operation, but to differential 5.0 4.0 15 25 35 45 55 65 AMBIENT TEMPERATURE - C 75 85 Figure 27. Maximum Die Power Dissipation vs. Ambient Temperature The above curve was calculated from (TJUNCTION, MAX - TAMBIENT) JA PD, MAX = As an example, if the AD8117/AD8118 is enclosed in an environment at 45C (TA), the total on-chip dissipation under all load and supply conditions must not be allowed to exceed 7.0 W. When calculating on-chip power dissipation, it is necessary to include the rms current being delivered to the load, multiplied by the rms voltage drop on the AD8117/AD8118 output devices. For a sinusoidal output, the on-chip power dissipation due the load can be approximated by PD, OUT = (VPOS - VOUTPUT, RMS) x IOUTPUT, RMS For nonsinusoidal output, the power dissipation should be calculated by integrating the on-chip voltage drop multiplied by the load current over one period. The user may subtract the quiescent current for the Class AB output stage when calculating the loaded power dissipation. For Rev. PrA | Page 24 of 32 Preliminary Technical Data each output stage driving a load, subtract a quiescent power according to PD, OUT, Q = (VPOS - VNEG) x IOUTPUT, QUIESCENT For the AD8117/AD8118, IOUTPUT, QUIESCENT = 1.65 mA for each single-ended output pin. For each disabled output, the quiescent power supply current in VPOS and VNEG drops by approximately 9 mA. VPOS AD8117/AD8118 PDQ, OUTPUT = (VPOS - VNEG) x IO, QUIESCENT PDQ, OUTPUT = (2.5 V - (-2.5V)) x (1.65 mA) = 8.25 mW There are 32 output pairs, or 64 output currents. nPD, OUTPUT = 64 x 8.25 mW = 0.53 W Step 4. Verify that the power dissipation does not exceed maximum allowed value. PD, ON-CHIP = PD, QUIESCENT + nPD, OUTPUT + nPDQ, OUTPUT PD, ON-CHIP = 2.5 W + 0.96 W - 0.53 W = 2.9 W IO,QUIESCENT QNPN VOUTPUT QPNP IOUTPUT From the figure or the equation, this power dissipation is below the maximum allowed dissipation for all ambient temperatures up to and including 85C. Short Circuit Output Conditions Although there is short-circuit current protection on the AD8117 outputs, the output current can reach values of 80 mA into a grounded output. Any sustained operation with too many shorted outputs can exceed the maximum die temperature and can result in device failure (see Absolute Maximum Ratings). IO,QUIESCENT VNEG Figure 28. Simplified Output Stage An example: AD8117, in an ambient temperature of 85C, with all 32 outputs driving 1 V rms into 100 supplies are 2.5 V. loads. Power Step 1. Calculate power dissipation of AD8117 using data sheet quiescent currents. We are neglecting VDD current as it is insignificant. PD, QUIESCENT = (VPOS x IVPOS) + (VNEG x IVNEG) PD, QUIESCENT = (2.5 V x 500 mA) + (2.5 V x 500 mA) = 2.5 W Crosstalk Many systems, such as broadcast video and KVM switches, that handle numerous analog signal channels, have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in close proximity in a system, as will undoubtedly be the case in a system that uses the AD8117/AD8118, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more crosspoint devices. Types of Crosstalk Crosstalk can be propagated by means of any of three methods. These fall into the categories of electric field, magnetic field, and sharing of common impedances. This section will explain these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Step 2. Calculate power dissipation from loads. For a differential output and ground-referenced load, the output power is symmetrical in each output phase. PD, OUTPUT = (VPOS - VOUTPUT, RMS) x IOUTPUT, RMS PD, OUTPUT = (2.5 V - 1 V) x (1 V/150 ) = 10 mW V/100 15 There are 32 output pairs, or 64 output currents. nPD, OUTPUT = 64 x 15 mW = 0.96 W Step 3. Subtract quiescent output stage current for number of loads (64 in this example). The output stage is either standing, or driving a load but the current only needs to be counted once (valid for output voltages > 0.5 V). Rev. PrA | Page 25 of 32 AD8117/AD8118 Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. The fact that the AD8117/AD8118 is a fullydifferential design means that many sources of crosstalk either destructively cancel, or are common-mode to the signal and can be rejected by a differential receiver. Areas of Crosstalk A practical AD8117/AD8118 circuit must be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that a system's crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. It is important to try to separate these two areas when attempting to minimize the effect of crosstalk. In addition, crosstalk can occur among the inputs to a crosspoint and among the outputs. It can also occur from input to output. Techniques will be discussed for diagnosing which part of a system is contributing to crosstalk. Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by |XT| = 20 log10 (ASEL(s) / ATEST(s)) where s = j is the Laplace transform variable, ASEL(s) is the amplitude of the crosstalk induced signal in the selected channel, and ATEST(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function Preliminary Technical Data of the magnitude of the test signal (to first order). In addition, the crosstalk signal will have a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 32 x 32 matrix of the AD8117, we can look at the number of crosstalk terms that can be considered for a single channel, say the IN00 input. IN00 is programmed to connect to one of the AD8117 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 31 inputs can be measured one at a time, while applying no signal to IN00. Then the crosstalk terms associated with driving a parallel test signal into all 31 other inputs can be measured two at a time in all possible combinations, then three at a time, and so on, until, finally, there is only one way to drive a test signal into all 31 other inputs in parallel. Each of these cases is legitimately different from the others and might yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers rather quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8117s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this will yield the worst crosstalk number, but this is not always the case, due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worstcase measure for any other one-channel or two-channel crosstalk measurements. Rev. PrA | Page 26 of 32 Preliminary Technical Data Input and Output Crosstalk Capacitive coupling is voltage-driven (dV/dt), but is generally a constant ratio. Capacitive crosstalk is proportional to input or output voltage, but this ratio is not reduced by simply reducing signal swings. Attenuation factors must be changed by changing impedances (lowering mutual capacitance), or destructive canceling must be utilized by summing equal and out of phase components. For high-input impedance devices such as the AD8117/AD8118, capacitances generally dominate input-generated crosstalk. Inductive coupling is proportional to current (dI/dt), and will often scale as a constant ratio with signal voltage, but will also show a dependence on impedances (load current). Inductive coupling can also be reduced by constructive canceling of equal and out of phase fields. In the case of driving low-impedance video loads, output inductances contribute highly to output crosstalk. The flexible programming capability of the AD8117/AD8118 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input pair (IN07 in the middle for this example) can be programmed to drive OUT07 (also in the middle). The inputs to IN07 are just terminated to ground (via 50 or 75 ) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT07 disabled. Since grounded IN07 is programmed to drive OUT07, no signal should be present. Any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven (they are all disabled). Thus, this method measures the all-hostile input contribution to crosstalk into IN07. Of course, the method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (far away from IN00), which is terminated to ground. Thus OUT07 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUT07 can be attributed to the output crosstalk of the other 16 hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the AD8117/AD8118 impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies the magnitude of the crosstalk will be given by |XT| = 20 log10[(RSCM) x s] where RS is the source resistance, CM is the mutual capacitance between the test signal circuit and the selected circuit, and s is the Laplace transform variable. From the equation it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8117 is specified with excellent differential gain and phase when driving a standard 150 video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8117. From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by |XT| = 20 log10 (MXY x s/RL) where MXY is the mutual inductance of output X to output Y and RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. PCB Layout Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas Rev. PrA | Page 27 of 32 AD8117/AD8118 that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8117/AD8118 is designed to help keep the crosstalk to a minimum. On the BGA substrate, each pair is carefully routed to predominately couple to each other, with shielding traces separating adjacent signal pairs. The ball grid array is arranged such that similar board routing can be achieved. Only the outer two rows are used for signals, such that vias can be used to take the input rows to a lower signal plane if desired. The input and output signals will have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The input and output signals surface at the input termination resistors and the output series backtermination resistors. To the extent possible, these signals should also be separated as soon as they emerge from the IC package. Preliminary Technical Data x 106 m/s), this means the AD8117/AD8118 should be no more than 1.5 cm after the termination resistors, and preferably should be placed even closer. The BGA substrate routing inside the AD8117/AD8118 is approximately 1 cm in length and adds to the stub length, so 1.5 cm PCB routing equates to d = 2.5 x 10 -2 m in the calculations. (2n + 1)VP 4d fpeak = , n = {0, 1, 2, 3, ...} PCB Termination Layout As frequencies of operation increase, the importance of proper transmission line signal routing becomes more important. The bandwidth of the AD8117/AD8118 is large enough that using high impedance routing will not provide a flat in-band frequency response for practical signal trace lengths. It is necessary for the user to choose a characteristic impedance suitable for the application and properly terminate the input and output signals of the AD8117/AD8118. Traditionally, video applications have used 75 single-ended enviroments. RF applications are generally 50 single-ended (and board manufacturers have the most experience with this application). CAT-5 cabling is usually driven as differential pairs of 100 differential impedance. For flexibility, the AD8117/AD8118 does not contain on-chip termination resistors. This flexibility in application comes with some board layout challenges. The distance between the termination of the input transmission line and the AD8117/AD8118 die is a high-impedance stub, and will cause reflections of the input signal. With some simplification, it can be shown that these reflections will cause peaking of the input at regular intervals in frequency, dependent on the propagation speed (VP) of the signal in the choosen board material and the distance (d) between the termination resistor and the AD8117/AD8118. If the distance is great enough, these peaks can occur in-band. In fact, practical experience shows that these peaks are not high-Q, and should be pushed out to three or four times the desired bandwidth in order to not have an effect on the signal. For a board designer using FR4 (VP = 144 In some cases, it is difficult to place the termination close to the AD8117/AD8118 due to space constraints, differential routing, and large resistor footprints. A preferable solution in this case is to maintain a controlled transmission line past the AD8117/AD8118 inputs and terminate the end of the line. This is known as fly-by termination. The input impedance of the AD8117/AD8118 is large enough and stub length inside the package is small enough that this works well in practice. Implementation of fly-by input termination often includes bringing the signal in on one routing layer, then passing through a filled-via under the AD8117/AD8118 input ball, then back out to termination on another signal layer. In this case, care must be taken to tie the reference ground planes together near the signal via if the signal layers are referenced to different ground planes. AD8117 IPn INn OPn ONn 75 Figure 29. Fly-by Input Termination. Grounds for the two transmission lines shown must be tied together close to the INn pin. If multiple AD8117/AD8118 are to be driven in parallel, a flyby input termination scheme is very useful, but the distance from each AD8117/AD8118 input to the driven input transmission line is a stub that should be minimized in length and parasitics using the discussed guidelines. When driving the AD8117/AD8118 single-endedly, the undriven input is often terminated with a resistance in order to balance the input stage. It can be seen that by terminating the undriven input with a resistor of one-half the characteristic impedance, the input stage will be perfectly balanced (37.5 , for example, to balance the two parallel 75 terminations on the driven input). However, due to the feedback in the input receiver, there is high-speed signal current leaving the undriven input. In order to terminate this high-speed signal, proper transmission-line techniques should be used. One solution is Rev. PrA | Page 28 of 32 Preliminary Technical Data to adjust the trace width to create a transmission line of half the characteristic impedance and terminate the far end with this resistance (37.5 in a 75 system). This is not often practical as trace widths become large. In most cases, the best practical solution is to place the half-characteristic impedance resistor as close as possible (preferably less than 1.5 cm away) and to reduce the parasitics of the stub (by removing the ground plane under the stub, for example). In either case, the designer must decide if the layout complexity created by a balanced, terminated solution is preferable to simply grounding the undriven input at the ball with no trace. AD8117/AD8118 While the examples discussed so far are for input termination, the theory is similar for output back-termination. Taking the AD8117/AD8118 as an ideal voltage source, any distance of routing between the AD8117/AD8118 and a back-termination resistor will be a stub that will create reflections. For this reason, back-termination resistors should also be placed close to the AD8117/AD8118. In practice, because back-termination resistors are series elements, their footprint in the routing is narrower and it is easier to place them close in board layout. Rev. PrA | Page 29 of 32 AD8117/AD8118 Preliminary Technical Data Figure 30. Evaluation Board Simplified Schematic Rev. PrA | Page 30 of 32 Preliminary Technical Data OUTLINE DIMENSIONS 31.00 BSC SQ 23 AD8117/AD8118 A1 CORNER INDEX AREA 6 4 2 22 20 18 16 14 12 10 8 21 19 17 15 13 11 9 5 3 7 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC BALL A1 INDICATOR TOP VIEW 27.94 BSC SQ 1.27 BSC BOTTOM VIEW DETAIL A *1.765 MAX 0.10 MIN DETAIL A 1.07 0.99 0.92 0.70 0.63 0.56 0.25 MIN (4x) 0.90 0.75 0.60 BALL DIAMETER COPLANARITY 0.20 SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-192-BAN-2 WITH THE EXCEPTION TO PACKAGE HEIGHT. Figure 31. 304-Lead Ball Grid Array, Thermally Enhanced [BGA_ED] Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range AD8117ABPZ -40C to +85C AD8118ABPZ -40C to +85C AD8117-EVAL NOTE: Z suffix denotes lead-free package. Package Description 304-Lead Ball Grid Array Package [BGA_ED] (31 x 31 mm) 304-Lead Ball Grid Array Package [BGA_ED] (31 x 31 mm) AD8117 Evaluation Kit Package Option SBGA-304 SBGA-304 Rev. PrA | Page 31 of 32 AD8117/AD8118 NOTES Preliminary Technical Data (c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06365-0-8/06(PrA) Rev. PrA | Page 32 of 32 |
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